Author

Anjunyi Fan

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Preprint Aug 2026

MCHA: A Memory-Centric Hierarchical Architecture for Parallel-Sequential Computing

The Memory-Centric Hierarchical Architecture (MCHA) is proposed, a reconfigurable hardware solution tailored for parallel-sequential execution that leverages a hierarchical communication strategy that facilitates distributed, inter-core data routing, thereby significantly reducing the bandwidth burden on the global mem...

Daijing Shi, Hongxiao Zhao, Yihan Fu et al. · 0 citations

Preprint Aug 2026

C2C-Explorer: An Exploration Framework for Chip-to-Chip Interconnect Architectures in LLM Cloud Computing Systems

C2C-Explorer is proposed, an adaptive Bayesian DSE framework that integrates a LLM-workload-driven traffic generator, a scalable interconnect simulator, and a metric-guided evaluator into a workload-to-hardware optimization pipeline, enabling systematic C2C architectural co-design under realistic LLM workloads.

Jia-Yi Li, Di Wu, Qingxu Li et al. · 0 citations