Open access
Aug 2026
An efficient reconfigurable floating point multiplier design for signal processing applications
The presented reconfigurable floating-point multiplier design offers a promising solution to meet the demanding computational requirements of modern signal processing systems, making it suitable for integration into high-performance digital signal processors and other embedded systems.
S. Singhal, S. K. Patel, Anurag Mahajan
· Review of Computer Engineeri... · 0 citations