Aysha Pareekutty

FPGA-Based Implementation and Simulation of a 3×3 Convolution Accelerator for Edge Detection

In an effort to mitigate processing delays and latency in the traditional edge detection in the vision based systems such as robotics and surveillance platforms, this paper attempts to introduce an FPGA-based 3×3 convolution accelerator. The proposed architecture employs a multiply-accumulate (MAC) unit and fixed-point...