Comparative energy awareness and performance analysis of ARM and RISC-V SHA-256 hardware acceleration on the RP2350
SHA-256 is a fundamental hashing algorithm in embedded security, authentication, data integrity verification, and hardware random number generation in resource-constrained systems. This paper presents a quantitative benchmarking study of SHA-256 on the Raspberry Pi RP2350, a microcontroller which has integrated both ARM Cortex-M33 and RISC-V Hazard3 cores on a single die, enabling a direct same-silicon architectural comparison under identical conditions. Throughput, execution time, current draw, and energy per kilobyte were measured across software and hardware-accelerated modes with and without Direct Memory Access on both cores, and against a software baseline on the predecessor RP2040. Hardware acceleration yielded speedups of 14.05\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times$$\end{document} and 13.58\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times$$\end{document} over software for the ARM and RISC-V cores respectively, with energy per KB reduced from approximately 25 \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$${\upmu }$$\end{document}J/KB to under 1.79 \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$${\upmu }$$\end{document}J/KB in both cases, while current draw remained stable between 17 and 18 mA across all configurations, indicating that efficiency gains are attributable to reduced execution time rather than lower active current. A counter-intuitive observation emerges from the DMA analysis: despite the ARM ecosystem’s significantly greater maturity in embedded bus integration, the ARM Cortex-M33 exhibits a larger DMA-induced throughput penalty (18.1%, factor of 1.221\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times$$\end{document}) than the newer RISC-V Hazard3 core (13.6%, factor of 1.157\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times$$\end{document}) when accessing the shared SHA-256 peripheral on identical silicon. To our knowledge, this is the first same-silicon comparison of ARM and RISC-V cryptographic acceleration with direct energy measurements, and the first published per-configuration energy characterization of the RP2350.