Register Transfer Level (RTL) code optimization is critical for meeting performance and power budgets in Field Programmable Gate Array (FPGA) design. Traditional approaches depend on expert knowledge or heuristics, which are time consuming and error prone. Therefore, recent research has explored using Large Language Mo...
Zhi-Hao Xu, Bi-Xin Li, Ran Yan et al.· ACM Transactions on Reconfig...· 0 citations
MSAQM is designed as a plug-in layer that enhances existing evaluators with mixed-source awareness while preserving their original general architecture quality evaluation capabilities, and improves the ability of existing evaluators to capture mixed-source-specific architecture quality changes while maintaining high co...
Chun-Guang Zhang, Bi-Xin Li, Hao Chen· International journal of sof...· 0 citations
Pretrained programming language models (PLMs) have shown strong performance in software engineering tasks, but remain vulnerable to adversarial attacks. Traditional methods rely on narrow, static perturbation strategies, leading to poor diversity and a combinatorial explosion of the search space when multiple operation...
Lulu Wang, Xiaoyi Wang, Xiaoning Du et al.· IEEE Transactions on Reliabi...· 0 citations
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