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Open access Sep 2026

An Observer–Data-Path Decoupled Time-Domain ADC with Three-Stage Digital Background Calibration in 28 nm CMOS

This paper presents an observer–data-path decoupled time-domain ADC with three-stage digital background calibration, designed and comprehensively verified through post-layout simulations in 28 nm CMOS for highly integrated micro-systems. In scaled nodes, the voltage-to-time converter front-end exhibits large-signal non...

Chuan Qin, Bo-Wen Liu, Run-Qiao Wang et al. · 0 citations

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