HAR-ASIC: A Configurable Edge-AI Human Activity Recognition Circuit for Ultra-Low Power Wearable Devices
We present an application-specific integrated circuit (ASIC) using digital hardware design to maximise energy-efficiency of human activity recognition (HAR) in autonomous wearable devices. The HAR-ASIC was designed in 22 nm technology and includes a battery of configurable, hardware-optimised feature extraction functio...