QiMeng-VPID: Verification-Grounded Port-Level Iterative Decomposition for Complex Verilog Generation
This work proposes VPID, a multi-agent framework for generating complex Verilog that achieves monotonic functional improvement and introduces an experience-guided refinement strategy that distills historical waveform mismatches into constraints, guiding the targeted debugging for the unverified ports.
Hongguang Wang, Jiaming Guo, Rui Zhang et al.
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