Donghyun Ryu

A Dual‐Programmable 2M NOR Flash Architecture for Energy‐Efficient In‐Memory Computing

ABSTRACT Conventional NOR Flash architectures employ either a 1M structure or a 1T–1M structure, the latter integrating an access transistor to enable selective program and erase operations. While the access transistor occupies a substantial portion of the 1T–1M cell area, it does not contribute to information storage....