F. Vartziotis

An Efficient and Power-Aware TAM Optimization and Test Scheduling Framework for DVFS-Based 3D SoCs

This work presents a power-friendly framework for efficient manufacturing test of dynamic voltage and frequency scaling (DVFS)-based 3D Systems-on-Chip (SoCs). The proposed approach employs a through-silicon via (TSV)-based inter-layer test architecture to enable compact and high-speed delivery of test data across stac...