G. Sai

Adaptive Precision Hierarchical Vedic Multiplier with CSA-Based 64-Bit Optimization for Low-Power FPGA Applications

In this paper, an energy-efficient Vedic multiplier design is presented through runtime-adaptive hierarchy. In the proposed architecture, the Urdhva-Tiryakbhyam Vedic algorithm has been implemented recursively from 2x2 to 32$\times$32 bit multiplication in a modular hierarchical fashion. In addition, the multiplier has...