Hui-Ji Zheng

A Deterministic FPGA-CPU Data Interaction Architecture with Cache-Aware Core Selection for Real-Time Systems

Achieving periodic, low-latency data transfer with deterministic timing guarantees between I/O devices (e.g., Field-Programmable Gate Arrays (FPGAs)) and hosts remains a fundamental challenge in real-time domains, including automated driving, high-frequency trading, and hardware-in-the-loop systems. Unpredictable commu...