RL-Driven 3D Clustering of Jscan Architecture with Routing and Area Optimization in Chiplet Sip
Three-dimensional stacked ICs introduce new Design-for-Test (DfT) challenges due to high power density, routing congestion, and cross-tier connectivity constraints. In this work We propose 3D Joint-Scan, a tier-aware DfT architecture that extends the 2D Joint-scan framework to multi-tier 3D ICs and integrates reinforce...