Jul 2026
A Low-Power Sparse Convolution Accelerator with Idle-First-Task-Assignment for Edge Vision
This paper presents a low-power sparse convolution accelerator for edge devices, fabricated and validated in a 16 nm process that adopts a bitmap-based format for compression in both data transmission and computation, effectively reducing memory and bandwidth overhead.
Jingyue Zhuge, Johannes Partzsch, Christian Mayr
· arXiv.org · 0 citations