Jude Haris

Automating FPGA Accelerator Design using Large Language Models

FAME: An FPGA-Based Platform for Approximate Multipliers Evaluation with Pattern-Guided DNN Retraining

The platform exploits the reconfigurable logic of Field-Programmable Gate Arrays to implement approximate multipliers directly in hardware, eliminating the need for LUT-based emulation on CPU/GPU platforms and thereby enabling efficient DNN inference while significantly reducing evaluation time on large datasets.

SECDA Design Suite: Efficient HW-SW Co-Design of DNN Accelerators for Edge Inference

The SECDA Design Suite is proposed, a set of specialized tools that enable an efficient design process for developing AI accelerators for edge inference, utilizing the SECDA design methodology, and provides a fully integrated environment that allows developers to design, deploy and evaluate new hardware architectures u...