Author

Kang Chen

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Open access Oct 2026

Towards Understanding the Bugs in Verilator, a Hardware Description Language Compiler

Verilator is the premier open-source Hardware Description Language (HDL) compiler. It transforms Verilog and SystemVerilog designs into optimized C++ or SystemC models, enabling high-speed, cycle-accurate simulation prior to large-scale production. As a cornerstone of the hardware verification ecosystem, the correctnes...

Song-Yan Jiang, Mao-Lin Sun, Kang Chen et al. · Proceedings of the ACM on So... · 0 citations