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Preprint Oct 2026

FAPO: Fanout-Aware Post-Mapping Optimization for LUT-Based FPGAs

Reducing logic depth during FPGA technology mapping does not necessarily eliminate fanout bottlenecks in the resulting LUT networks.Replicating heavily loaded LUTs can alleviate these bottlenecks, but the added copies consume area and may increase upstream loading. We propose FAPO, a mapper-independent post-mapping opt...

Xiao-Yu Hao, Ke-Ren Zhu · 1 citation
Preprint Oct 2026

Safe Hypergraph Contraction via Capacity-Aware Repair Certificates

Multilevel partitioners shrink circuit hypergraphs through vertex contractions, yet a contraction that satisfies block capacity can still eliminate every optimal balanced bipartition. We develop certified safe coarsening (CSC) to identify contractions that preserve an optimum without computing that optimum. CSC certifi...

Yu-Zhou Deng, Xin-Yi Yang, Ke-Ren Zhu · 0 citations
Jul 2026

Provably Good Prim-Dijkstra Revisited: New Theory and a Practical Algorithm for a Classical VLSI Routing Problem with LLMs

Large language models may make precise but dormant algorithmic problems practical to revisit, and may expose new paths toward fundamental ones. We demonstrate this possibility through Prim-Dijkstra routing, a classic VLSI problem whose terminal-only Manhattan complexity remained open despite decades of practical work....

Keren Zhu · 1 citation

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