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Open access Sep 2026

HAR-ASIC: A Configurable Edge-AI Human Activity Recognition Circuit for Ultra-Low Power Wearable Devices

We present an application-specific integrated circuit (ASIC) using digital hardware design to maximise energy-efficiency of human activity recognition (HAR) in autonomous wearable devices. The HAR-ASIC was designed in 22 nm technology and includes a battery of configurable, hardware-optimised feature extraction functio...

Tobias Peikenkamp, Daniel Konegen, Jacob Göppert et al. · 1 citation

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