Padala Jayakrishna

Synergistic Hybrid GDI–CNTFET Architecture for Low-Power and Area-Optimized Nanoscale VLSI Circuits

As CMOS technology continues to expand to a deep sub-micron scale, standard designs are confronted with many challenges in terms of energy dissipation, leakage currents and area. Although GDI logic minimizes the number of transistors and CNTFET offers improved transport performance, it is on its own that it provides op...