Modular Real-Time FPGA Implementation of SDFT Pre-Processing and Hardware-Optimized MLP Inference for Visible Light Positioning Receivers
This paper presents an FPGA feasibility study of two digital processing blocks for a future real-time Visible Light Positioning (VLP) receiver: a Sliding Discrete Fourier Transform (SDFT) stage for carrier-magnitude extraction and a hardware-optimized Multi-Layer Perceptron (MLP) inference engine for coordinate estimat...