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S. Singhal

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Open access Aug 2026

An efficient reconfigurable floating point multiplier design for signal processing applications

The presented reconfigurable floating-point multiplier design offers a promising solution to meet the demanding computational requirements of modern signal processing systems, making it suitable for integration into high-performance digital signal processors and other embedded systems.

S. Singhal, S. K. Patel, Anurag Mahajan · 0 citations

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