Author

Shixuan Sun

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Preprint Aug 2026

A Thread-Register Decoupled GPU Execution Model for Efficient Tensor Computation

This work proposes FIBER, a new architecture that extends the GPU SIMT (single instruction, multiple thread) model, and extends the ISA, microarchitecture, and compiler to realize shared-register addressing, conflict-free operand delivery, and fiber-based program mapping.

Zihan Liu, Jingwen Leng, Yangjie Zhou et al. · 0 citations

Jul 2026

GPU-Tile-Sim: A Tile-Centric GPU Simulation Framework for LLM Hardware-Software Co-Design

This work proposes GPU-Tile-Sim, a tile-centric GPU simulation framework for LLM hardware-software co-design that represents kernel execution as a warp-level tile graph whose nodes capture tile-level operations and whose edges encode data and ordering constraints.

Yitong Ding, Jiawei Huang, Renyang Guan et al. · arXiv.org · 2 citations