Sirui Wang

FPGA-Based Bilinear Interpolation Image Scaler with Q8 Fixed-Point Arithmetic and Hardware-Software Co-Verification

Image scaling serves as a critical performance bottleneck in real-time video pipelines powering multi-resolution embedded display systems. The design integrates a dual ping-pong line buffer architecture to deliver four pixels per clock cycle, paired with a digital differential analyzer (DDA) for precise sub-pixel coord...