Author

Surya Selvam

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Preprint Oct 2026

TADA: Technology Aware DNN Accelerator Performance and Energy Estimator

Deep neural network (DNN) accelerators for edge inference must meet tight energy, latency, and area (EDP) constraints, and their optimal hardware architecture and dataflow configuration is typically identified through design space exploration (DSE). However, on-chip memory technology including cell type, bank organizat...

Tanvi Sharma, Surya Selvam, Anand Raghunathan et al. · 0 citations

#artificial intelligence Preprint Oct 2026

Agentic Design Space Exploration for Joint Hardware Configuration Selection and Mapping of AI Inference Workloads on Heterogeneous Edge SoCs

Modern edge Systems-on-Chip (SoCs) integrate heterogeneous processing units (PUs) such as CPUs, GPUs, and NPUs, each with distinct performance and energy characteristics. Deploying AI inference workloads on them under real-time latency and energy constraints requires jointly mapping workloads to PUs and configuring eac...

Geetha Prasuna Yarramneni, Surya Selvam, W. Haensch et al. · 0 citations