Post-route FPGA timing closure remains expert-dependent and computationally expensive. We present LATCH (LLM-Assisted Timing Closure Harness), a two-layer framework that separates large language model (LLM) orchestration from deterministic FPGA implementation and evaluation. Across sixteen designs and seven LLMs, a sin...
Shuang-Long Gu, Matthew Youngman, Yu-Qin Zhao et al.· 0 citations
Optoelectronic resistive random-access memory elements (ORRAM) are critical emerging devices that leverage photonic technologies to bring the advantages of optical programming to traditionally electronic memristive platforms for neuromorphic computing and artificial intelligence. In this work, a free-space optic micro-...
A. Adair, J. Robertson, A. Tsiamis et al.· 0 citations
Resistive random access memory (RRAM) devices, also known as memristors, are highly dependent on fabrication, location on the wafer, and measurement protocols. However, openly available large-scale memristor datasets remain scarce, particularly those that combine experimental metadata with electrical measurements and p...
Gan-Ping Lai, Guoyang Huang, D. Yadav et al.· 0 citations
Electronic design automation (EDA) has advanced engineering productivity through successive generations of tooling that progressively automate synthesis, optimisation, and verification. Large language models (LLMs) extend this trajectory by enabling direct translation from design intent to hardware implementations. In...
Matthew Youngman, Cristian Sestito, T. Prodromakis· 0 citations
Analog circuit sizing remains a challenging and time-consuming task due to the large design space, strong performance trade-offs, and increasing circuit complexity in scaled technologies. Although recent large language model (LLM)-based methods show promise in improving sample efficiency and interpretability, existing...
Yi-Jia Hao, Pratibha Verma, Dong-Xu Guo et al.· 0 citations
It is argued that progress in vision generative AI has been driven by output quality, with hardware evolving reactively to accommodate growing model demands, making generative AI deployment sustainable and accessible across a much broader range of platforms.
Eleni Tselepi, Cristian Sestito, Shady O. Agwa et al.· 0 citations
Gen-TAS, a knowledge-grounded LLM framework for user-specific FPGA-GPP task allocation, is proposed by combining task-graph analysis with RAG, which grounds LLM reasoning in historical implementation knowledge and generates multiple explainable strategies tailored to the specified objectives.
Mary Kong, Yu-Qin Zhao, Semih Vazgecen et al.· 0 citations
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