Xiao-Yu Hao

FAPO: Fanout-Aware Post-Mapping Optimization for LUT-Based FPGAs

Reducing logic depth during FPGA technology mapping does not necessarily eliminate fanout bottlenecks in the resulting LUT networks.Replicating heavily loaded LUTs can alleviate these bottlenecks, but the added copies consume area and may increase upstream loading. We propose FAPO, a mapper-independent post-mapping opt...