Enabling Spatially Fine-Grained DVFS in Neural Processing Units for Energy-Efficient LLM Serving
eNPU uses a compiler-driven two-level greedy search to co-optimize instruction scheduling and per-component V/$f$ selection under SLO constraints, and introduces lightweight cross-domain communication mechanisms to mitigate synchronization overheads across components, and extends the NPU ISA for sub-mu DVFS control.