Author

Zhaoyang Yu

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Preprint Sep 2026

VSpector: Specification-Driven Bug Detection for RISC-V CPUs

VSpector is presented, a specification-driven bug detection pipeline that directly checks whether CPU register-transfer level (RTL) implementations adhere to official specification rules, without requiring specialized construction of reference models, formal properties, or custom bug patterns.

Tian-Yu Jia, Zhao-Yang Yu, Yuan-Liang Chen et al. · 0 citations

#artificial intelligence Preprint Aug 2026

SMTrap: Cost-Effective DoS Attacks Against Large Reasoning Models via SMT Conflict Guidance

A novel, model-feedback-free LRM-DoS paradigm that employs the conflict count derived from an Satisfiability Modulo Theories (SMT) solver as a low-cost external signal to guide the synthesis of inference-heavy Constraint Satisfaction Problem (CSP) instances.

Jian Yang, Zhenqi Feng, Zhaoyang Yu et al. · 0 citations