Author

Zi-Yang Zheng

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#artificial intelligence Preprint Sep 2026

LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks

LevelSyn is a novel physical-aware logic synthesis framework that integrates hierarchical representation learning with a wirelength-driven optimization engine that significantly outperforms state-of-the-art methods on the EPFL benchmark suite.

Jing-Yi Zhou, Zhengyuan Shi, Zi-Yang Zheng et al. · 0 citations

#artificial intelligence Preprint Aug 2026

Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits

DeepSeq3 is introduced, a novel hierarchical framework that abstracts circuits into a two-level representation: fine-grained combinational subgraphs partitioned by flip-flops (FFs) and a high-level Super-Node Graph (SNG) that models the register-transfer structure.

Jing-Yi Zhou, Zhengyuan Shi, Jiaying Zhu et al. · 0 citations