Evaluating Link-level Lossless Mechanisms in AI Networks

Reliable RDMA Over Lossy Fabrics via Data-Control Partitioning

Due to the high operational complexity and limited deployment scale of lossless RDMA networks, the community has been exploring efficient RDMA communication over lossy fabrics. State-of-the-art (SOTA) lossy RDMA solutions implement a simplified selective repeat mechanism in RDMA NICs (RNICs) to enhance loss recovery efficiency. However, these solutions still face performance challenges, such as unavoidable ECMP hash collisions and excessive retransmission timeouts (RTOs). In this paper, we enhance RDMA reliability with the goals of being independent of PFC, compatible with packet-level load balancing, free from RTO, and friendly to hardware offloading. To this end, we propose DCP, a transport architecture that co-designs both the switch and RNICs, fully meeting the design goals. At its core, DCP-Switch introduces a simple yet effective lossless control plane, which is leveraged by DCP-RNIC to enhance reliability support for high-speed lossy fabrics, primarily including header-only-based retransmission and bitmap-free packet tracking. We prototype DCP-Switch using P4 switch and DCP-RNIC using FPGA. Extensive experiments demonstrate that DCP achieves $1.6\times $ and $2.1\times $ performance improvements, compared to SOTA lossless and lossy RDMA solutions, respectively.

CSIG: Congestion Signaling for Datacenter Transports

Optimizing burst-heavy datacenter workloads necessitates finegrained network control and visibility. We introduce CSIG, a protocol that delivers precise, multi-bit bottleneck congestion signals via a fixed-length Ethernet header. The architecture captures μsgranularity switch metrics, such as available bandwidth, and signals them to end-hosts using in-band, line-rate operations. We propose Fast Ramp-Up, a congestion control primitive that leverages these bottleneck signals to reduce median RPC latency by 20% and unclaimed bandwidth by 60% in production. Beyond transport-level performance, CSIG enables flow-aware observability by embedding μs-scale metrics into every packet, allowing individual application transfers to pinpoint their bottleneck location, such as the topology tier limiting their performance. CSIG thus transforms network telemetry from post-hoc correlation into a real time, context-aware capability. We demonstrate CSIG's broad deployability by validating it across five generations of commodity switch hardware (up to 102.4 Tbps), four NIC generations, and five transport stacks. Our design proves that a streamlined Layer 2 approach, focusing exclusively on the principal path bottleneck, provides transport-agnostic gains without requiring forklift hardware upgrades.

Controlling Adaptive HARQ Erasure Coding for Real-Time Transport Under Channel Model Mismatch

of a CBQ router

Quanta: Scaling Packet-Level Network Simulation by Exploiting Execution Redundancy

Packet-level network simulation provides high-fidelity modeling but suffers from severe scalability bottlenecks. Existing scaling approaches remain inefficient for modern data-center and AI-training networks. Spatial parallelism requires substantial hardware resources, while temporal-skipping approaches become less effective under bursty traffic. We observe that homogeneous data-center deployments introduce substantial execution redundancy during simulation. This paper presents Quanta, a redundancy-aware simulation framework that eliminates repeated execution in packet-level simulation. Quanta reduces the dependence of simulation cost on physical network scale. Our evaluation shows that Quanta accelerates large-scale simulations by up to 90 × , synergizes with parallel execution for a 320 × combined speedup.

Extending Low Latency Service Across the Internet

Protocols such as L4S for low latency network services have attracted growing interest from major industry stakeholders such as Comcast, Apple, T-Mobile, and NVIDIA. However, L4S requires isolation between L4S flows and classic flows in order to maintain its low latency benefits and safe coexistence. The L4S architecture uses a DualPI2 AQM mechanism to provide this isolation when the bottleneck occurs at the home access link. In practice, however, bottlenecks may also occur at other locations in the network, such as peering points, ingress to wide area networks, or occasionally congested links in the core, where deploying DualPI2 AQM is not feasible. Without a solution to this problem, L4S may struggle to gain deployment, since its benefits may remain limited without end-to-end support. To address this challenge, we propose a deployment strategy that reduces the need to upgrade expensive core routers by using existing networking mechanisms such as BGP communities, SRv6, and priority queues with rate caps. We demonstrate the feasibility of this approach through large scale experiments on the FABRIC testbed. Our results demonstrate a practical deployment strategy for extending low latency service across the Internet, even across independently administered networks.