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Human-AI Interaction: Evaluating LLM Reasoning on Digital Logic Circuits and the Perception-Correctness Gap

Sep 2026 · SN Computer Science · Vol 7 · 0 citations · 27 references
Explainable Artificial Intelligence (XAI)

TL;DR

Evaluating three widely used LLMs on 10 undergraduate-level digital logic questions spanning non-standard counters, JK-based state transitions, timing diagrams, frequency division, and finite-state machines suggests that they may be unreliable for core digital logic topics and can inadvertently reinforce misconceptions in undergraduate instruction.

Abstract

Large Language Models (LLMs) are increasingly used by undergraduate students as on-demand tutors, yet their reliability on circuit- and diagram-based digital logic problems remains unclear. This study presents a human- AI study evaluating three widely used LLMs (GPT, Gemini, and Claude) on 10 undergraduate-level digital logic questions spanning non-standard counters, JK-based state transitions, timing diagrams, frequency division, and finite-state machines. Twenty-four students performed pairwise model comparisons, providing per-question judgments on (i) preferred model, (ii) perceived correctness, (iii) consistency, (iv) verbosity, and (v) confidence, along with global ratings of overall model quality, satisfaction across multiple dimensions (e.g., accuracy and clarity), and perceived mental effort required to verify answers. An independent judge-based evaluation against official solutions for all ten questions is applied to benchmark technical validity, using strict correctness criteria. Results reveal a consistent gap between perceived helpfulness and formal correctness: for the most sequentially demanding problems (Q1- Q7), none of the evaluated LLMs matched the official answers, despite producing confident, well-structured explanations that students often rated favorably. Across Q1-Q7, 68% of student judgments labeled incorrect responses as correct despite no model matching the official solutions. Error analysis indicates that models frequently default to canonical textbook templates (e.g., standard ripple counters) and struggle to translate circuit structure into exact state evolution and timing behavior. These findings suggest that, without verification scaffolds, LLMs may be unreliable for core digital logic topics and can inadvertently reinforce misconceptions in undergraduate instruction.

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