Hardware implementation for traffic sign classification system using convolutional neural network
Abstract
The deployment of deep learning models for Traffic Sign Recognition Systems (TSRS) in real-world Advanced Driver Assistance Systems (ADAS) is often constrained by the limited computational resources of embedded platforms. This paper presents a comprehensive hardware-software co-design solution for implementing a lightweight, high-performance Convolutional Neural Network (CNN) on a Field-Programmable Gate Array (FPGA). A ResCoNN-based architecture was modified for the 43-class German Traffic Sign Recognition Benchmark (GTSRB) and optimized using 8-bit post-training static quantization. A pipelined hardware accelerator was designed, with its performance enhanced through a comparative analysis of loop unrolling strategies. The resulting system achieves a classification accuracy of 95.53% and an impressive throughput of 247 frames per second (FPS). This high performance is achieved while consuming 15,830 LUTs, 19,284 FFs, 209 BRAMs, and 123 DSPs. The lightweight model architecture enables all weight data to be stored in on-chip BRAM, thereby eliminating external memory access latency. This work demonstrates a practical and balanced solution that surpasses many state-of-the-art implementations in speed and efficiency, confirming its viability for resource-constrained automotive applications.