Aug 2026· Analog Integrated Circuits and Signal Processing· Vol 128· 0 citations· 41 references
TL;DR
This paper focuses on pre-silicon-based HT detection and machine learning techniques that automate feature data during training to identify HTs without the use of a golden chip and demonstrates the effectiveness of optimal feature extraction for Trojan detection.
The globalization of integrated-circuit design and fabrication has increased the risk of malicious hardware modifications. This paper presents a non-invasive electromagnetic side-channel framework for hardware Trojan detection using Deep Support Vector Data Description (Deep SVDD). Electromagnetic emissions from a devi...
Vasikarla Renuka, T Swathi, Megavath Ravindar, Ramavath Sharath· International Journal of Adv...· 0 citations
With the globalization of integrated circuit (IC) supply chains, hardware Trojans (HTs) have posed severe security threats to ICs and the entire information infrastructure. Design-time HT detection is recognized as a critical proactive countermeasure; however, existing feature-based analysis methods suffer from inheren...
Yan-Jiang Liu, Li-Chao Zhang, Jun-Wei Li et al.· International Test Conferenc...· 0 citations
A stacked ensemble ML model combining Random Forest and Logistic Regression and Logistic Regression as a meta-classifier, while Extreme Gradient Boosting as a meta-classifier is proposed in this study to improve software system cyberattack detection.
Anshika Sharma, S. Rani· SN Computer Science· 0 citations
A deep learning anomaly identification model integrating embedded representation, bidirectional recurrent networks/Transformer encoding, attention weighting, and adaptive threshold control was constructed, providing a method reference for building interpretable and scalable intelligent security protection systems in co...
Shuai Long, Zeliang Xiao· International Conference on...· 0 citations
It is shown that RTL Trojans exhibit stable structural and signal-flow patterns post-synthesis, enabling effective detection through targeted heuristics rather than generic ML feature learning.
Navid Nader Tehrani, Azadeh Davoodi, R. Topaloglu· 0 citations
This paper shows that a single architecture can be used to build fast and ultra-low-power AES hardware efficiently on FPGA, ASIC, and RISC-V. The system uses automated design exploration and adaptive decision-making to choose architectural parameters like pipeline stages, S-Box implementation, and voltage-frequency sca...
Durgam Muskinamma, Gutti Nagaswetha· Natural Resources for Human...· 0 citations
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