High-Performance Implementation of AES-128 Encryption and Decryption on FPGA Using Pipeline Architecture with UART Communication

Abstract

With the growing number of sophisticated cryptographic attacks and the need for high-speed secure data communications, the design and implementation of hardware-based encryption appears inevitable. This paper aims to design a highspeed pipelined Advanced Encryption Standard (AES-128) architecture using the latest 28 nm Xilinx Artix-7 Field Programmable Gate Array (FPGA). Particularly, we envisioned a pipelined AES architecture with parallelised pipelined and expanded key setup stages to maximise the throughput. To validate the proposed ideas, the architecture was carefully described in Verilog Hardware Description Language (HDL). Furthermore, both encryption and decryption pipelined round components were replicated and encapsulated into a single module. This module was also interconnected with a newly proposed real-time UART IP core for immediate hardware debugging. Additionally, functional verification based on NIST standard test vectors was utilised to verify perfect data recovery with no timing violations. Finally, the Place and Route on the target device reported the logic utilisation and throughput of 59.1 Mbps (13.1 Mbps) for encryption (decryption).