A 28-nm PVT Inner-Tracking Time-Domain Compute-In-Memory Macro for Edge-AI Devices

Abstract

This article presents an energy-efficient and process-, voltage-, and temperature (PVT)-robust time-domain (TD) compute-in-memory (CIM) macro for edge artificial intelligence (AI) devices. It features: 1) a PVT inner-tracking (PIT) technique that aligns the PVT responses of TD computation and TD quantization, delivering inherent robustness without incurring extra power or circuit overhead; 2) a scalable global timer (SGT) that eliminates standard quantization within the CIM array, enabling scalable precision for varying accumulation sizes while alleviating energy and area bottlenecks; and 3) a reconfigurable pipelined cascading (RPC) mechanism that allows for flexible accumulation sizes without sacrificing utilization and speed, thus narrowing the gap between peak and average energy efficiency. Fabricated in a 28-nm CMOS process, the prototype TD-CIM macro achieves an energy efficiency of 82.2–236.5 TOPS/W in 4-bit mode and 20.4–58.7 TOPS/W in 8-bit mode. Furthermore, the 8-bit mode demonstrates an accuracy loss of less than 1.12% across various networks on ImageNet, even with wide variations in supply voltage and temperature.