Aug 2026· Midwest Symposium on Circuits and Systems· pp. 445-449· 0 citations· 16 references
Abstract
Current-domain compute-in-memory (CIM) architectures offer a promising pathway to reduce data movement and eliminate costly data conversion overheads in edge AI systems. However, conventional resistive crossbar implementations rely heavily on peripheral circuits such as analog-to-digital converters (ADCs), which dominate system energy and latency. This work presents a fully current-domain CIM architecture that performs matrix-vector multiplication (MVM) through direct summation of weighted input currents using current mirrors, eliminating the need for intermediate voltage domain conversion and ADCbased readout. Synaptic weights are implemented using a two-ReRAM voltage-divider structure that improves robustness to device variability by ensuring rail-to-rail switching behavior. An integrated current-domain non-linear activation stage suppresses leakage and background light currents. Circuit-level simulations demonstrate 9.6× improvement in energy efficiency and $8.3 \times$ reduction in latency compared to an ADC-based baseline. The proposed architecture enables scalable and energy-efficient current-domain in-memory computing for edge AI applications.
Charge-CIM addresses the bottleneck in ACiM accelerators by using switched-capacitor charge redistribution as a unified computing and conversion substrate, reducing both standalone converter overhead and intermediate ADC invocations.
Zihao Xuan, Ye-Wen Li, Jia Chen et al.· 0 citations
This work presents a schematic-level digital near-memory computing architecture based on a 1-Transistor-3-Resistor (1T3R) bit-slicing scheme for 3-bit signed weight storage and indicates that the proposed architecture can maintain functional classification capability under 3-bit weight and 2-bit input constraints.
Zeyuan Hou, Xiao-Meng Wang, Yang Yi· Journal of Electronics and E...· 0 citations
Modern edge devices increasingly require real-time adaptation to their environment without relying on cloud-based updates, which can introduce latency and security risks. To meet these demands, memory-augmented neural networks (MANNs) have gained traction for enabling adaptive on-device learning. Hardware implementatio...
Changhoon Joe, K. Byun, Min-Seung Kang et al.· npj Unconventional Computing· 0 citations
Energy-efficient neural computing is increasingly limited not by computational throughput but by memory access and data movement. In-memory computing architectures offer a promising solution by collocating storage and computation, yet their practical realization remains constrained by static power dissipation, thermal...
Junsu Yu, Hwiho Hwang, H. Kim et al.· Nano Convergence· 0 citations
SRAM-based computing-in-memory (SRAM-CIM) alleviates the memory-wall bottleneck of the von Neumann architecture, enabling energy-efficient AI edge computing. Current-domain CIM schemes suffer from degraded linearity at low supply voltages, whereas time-domain CIM schemes are highly sensitive to process, voltage, and te...
Xiao-Bo Gong, Bin Qiang, Zi-Li Jiang et al.· IEEE Transactions on Circuit...· 0 citations
Analog compute-in-memory (CIM) enables energy-efficient model acceleration, but its reliance on ADC-based readout, which directly quantizes noisy column currents, makes inference accuracy highly sensitive to analog read noise, active-row scaling, and ADC precision. In this paper, we present NOVA-CIM, a noise- and corre...
Jia-Chen Ren, Wen-Shuai Yao, Hao-Bo Liu et al.· 0 citations
We use cookies to run the site and, with your consent, for analytics and to show ads.
See our Cookie Policy.