HOUTU: Hardware-Software Co-Design of FPGA-based Spiking Neural Network Accelerator for Temperature Field Digital Twin Reconstruction

Abstract

Temperature field digital twin reconstruction aims to recover the full-field temperature distribution from sparse sensor measurements, which is critical for real-time thermal monitoring of electronic systems. Deploying deep neural networks on edge devices remains challenging due to high computational cost and energy consumption. Spiking neural networks (SNNs) offer inherent energy efficiency through binary spike-based communication. In this paper, we propose a hardware-software co-design framework for FPGA-based SNN temperature field reconstruction. On the algorithm side, UNet and SegNet are trained and then converted to Spiking-UNet and Spiking-SegNet by replacing ReLU activations with Integrate-and-Fire (IF) neurons, followed by surrogate gradient fine-tuning. We evaluate time step configurations (T=3, 4, 8) and 16-bit fixed-point quantization. On the hardware side, we design an SNN accelerator featuring a 32-PE array with ping-pong weight buffering, supporting four operators: 3×3 convolution, average pooling, deconvolution, and 1×1 convolution. The system is validated on a Xilinx AXU15EG FPGA. Spiking-UNet achieves an MAE of 2.366 K, 4.292 FPS, and 2.436 W power; Spiking-SegNet achieves 3.302 K MAE at 5.4 FPS with 2.185 W.