Research on a highly reliable startup and loading technology for software-defined satellite payloads

Abstract

Software-defined satellite technology breaks the strong coupling between satellite hardware platforms and application software. This technology significantly enhances the flexibility and reconfigurability of satellite systems. However, it is important to note that in hostile onboard environments characterized by single-event effects and space radiation, the reliability of program loading for chips such as FPGAs, CPUs, DSPs, and AI processors has become a critical bottleneck. This bottleneck limits the engineering application of this technology. To address the issue above, this paper proposes and implements a high-reliability loading and startup technique for onboard software-defined functions. The proposed technique employs a separated architecture with a control unit and a computing unit, and designs a three-level controllable loading mechanism. The first level achieves high-reliability loading of the core software in the control unit. The second level enables monitorable and reconfigurable multiple loading of the FPGA module in the computing unit. The third level implements a selective loading of the CPUs, DSPs, and AI modules in the computing unit, which performs loading operations at least three times by default or up to a preset maximum number of loading attempts. The proposed technique supports real-time monitoring, fault localization, and repeated loading during the loading process, thereby effectively solving the high-reliability challenge in the software loading phase. The experimental results show that a domestic hardware platform can achieve stable and reliable startup and loading. Such results provide solid technical support for the engineering application of software-defined satellites.