Nov 2026· IEEE transactions on power electronics· Vol 41, pp. 19487-19498· 0 citations· 25 references
Abstract
With the rapid growth of artificial intelligence and data center computing power demands, power supply systems face dual challenges of high power density and high efficiency. These trends drive the bus voltage toward high-voltage direct current. However, existing transformer solutions struggle to simultaneously meet the requirements of extremely high step-down ratios and compact layouts. This article proposes a magnetically integrated fractional-turn matrix transformer with a high step-down ratio for high-performance DC–DC conversion. Based on the flux cancelation principle, the proposed scheme systematically integrates discrete fractional-turn units into a single high-density magnetic component. To address circuit-magnetic compatibility challenges during integration, a vertical excitation loop is innovatively designed. A “flux-free region” via-hole is constructed in the center of the magnetic plate. This structure accurately reconstructs the magnetic coupling characteristics of fractional turns. Meanwhile, it forms a low-impedance current path and effectively eliminates parasitic interference in the drive loop. Based on this scheme, a 1.2-kW, 1-MHz LLC-DCX resonant converter prototype is designed and fabricated. This prototype achieves direct conversion from 400 to 6.25 V (64:1). Experimental results demonstrate that the prototype achieves an ultra-high power density of 2.5 kW/in3 and a peak efficiency of 97.40%. These results verify the superiority of the proposed scheme for next-generation high-performance computing applications.
This article proposes a high-power-density flux-split coupled-transformer voltage regulator (FS-CTVR) with improved dynamic response for 48 V data center power supplies. The topology resolves the large winding loss and insufficient dynamic performance of convenitional current Doubler rectifier (CDR) converters. A magnetically integrated transformer with primary flux splitting and secondary parallel current sharing is developed to achieve a high turns ratio, reduce winding footprint and current stress, and mitigate winding losses. Additional PCB winding layers form a common coupling loop for multiphase CDR transformers, which reduces transient output inductance and improves dynamic response. Comprehensive analysis, design and performance evaluation of the FS-CTVR are presented. A two-module parallel prototype (54 V input, 0.9 V output) is built and tested. Each module delivers 150 A full-load current, 88.6% full-load efficiency and 1687 W/in3 power density, with a dynamic voltage fluctuation of 88 mV. Experimental results validate the feasibility and superior performance of the proposed topology.
Yijie Wang, Zikang Li, Jingyang Tan et al.· IEEE transactions on power e...· 0 citations
This article introduces a novel ultra-high voltage gain DC-DC converter with a low component count, designed for renewable energy applications. In the presented topology, a three-winding coupled-inductor (TWCI) and a switched-capacitor network are embedded within a classic quadratic boost converter. This arrangement yields high voltage gain, ensures continuous low-ripple input current, and preserves a common ground between the source and the load. Due to its trans-inverse feature, the circuit achieves ultra-high voltage gain even with a very low turns ratio in the TWCI. The topology also features current sharing between the TWCI and the main power switch, which significantly reduces power losses in the main power switch and coupled-inductor device. To limit voltage stresses on the active switches, the circuit integrates two passive regenerative clamp circuits, with the switches themselves operated using simultaneous switching patterns. The paper provides detailed steady-state analysis, power loss calculations, comparative evaluation, and design considerations. Finally, a laboratory prototype rated at 200 W has been implemented to verify the theoretical analysis, achieving a very high voltage conversion from 20 V input to 400 V output.
By integrating a three-winding coupled inductor (TWCI) with voltage multiplier cells, this study proposes a quadratic DC-DC converter that achieves ultra-high voltage gain while maintaining continuous input current and a common ground. The proposed coupled-inductor topology is specifically engineered to minimize both voltage and current stresses across all circuit components, thereby enhancing overall performance and enabling potential cost reductions. Enhanced design flexibility is a key feature of the proposed configuration, particularly because the secondary winding of the TWCI operates in a semi-trans-inverse manner, allowing high voltage gains to be realized even with a very low turns ratio. Regenerative passive clamp circuits are incorporated to recover the leakage energy of the TWCI and to limit voltage stresses on the active switches, which are driven with simultaneous switching patterns. The converter's vertical structure further alleviates semiconductor voltage stress, while intrinsic current sharing between the TWCI and the input inductor substantially reduces power dissipation in the main power components. Additionally, turn-off switching losses of both active switches are minimized via a quasi-resonant cell. The paper presents a comprehensive steady-state analysis, detailed power loss evaluation, a comparative study with existing topologies, and key design guidelines. All theoretical contributions are conclusively validated through experimental results obtained from a 200 W hardware prototype, converting a 25 V input to a 400 V output.
Mohammed Jawad Kadhim, M. Moazzami, G. Shahgholian et al.· Scientific Reports· 0 citations
Traditional high step-up DC–DC converters for renewable energy sources (RESs) often suffer from critical limitations, including the requirement for extreme duty cycles to achieve high voltage gains, elevated voltage and current stresses on semiconductors, and the imposition of full output voltage on the output capacitor and diodes. This paper presents a single-switch, non-isolated high step-up DC–DC converter that overcomes these challenges by combining a coupled inductor (CI) and voltage multiplier (VM) cells with a modified buck–boost–converter-based structure. The proposed topology achieves a high voltage conversion ratio while effectively distributing voltage stresses among the circuit components. The coupled inductor mitigates diode reverse-recovery problems, and a passive clamp circuit suppresses voltage spikes arising from leakage inductance, thereby reducing switch stress and enhancing its efficiency. Comprehensive theoretical analysis, along with comparative evaluations against similar configurations, demonstrates that the proposed converter delivers high voltage gain across the full duty-cycle range with the minimum normalized switch voltage stress. It also exhibits among the lowest diode voltage stresses and utilizes relatively low-value passive components, all within a simple structure employing only one power switch and one magnetic core. Four extended topologies utilizing an extra inductor or coupled inductor alongside an extra power switch, offering one more degree of freedom are also developed, analyzed in their various operational states, and simulated in this paper. Experimental validation of the main topology, operating at 300 W and 50 kHz while stepping up 30 V to 380 V, confirms the provided analyses and proper practical performance.
Soheil Hasani Sangani, Mohsen Seyyedhosseini, R. Beiranvand et al.· IEEE Access· 0 citations
High-efficiency and high-power-density point-of-load (POL) converters are critical for data center power supplies. Although hybrid resonant switched-capacitor (ReSC) converters can substantially reduce the volume of passive components, they often suffer from severe efficiency degradation when the switching frequency mismatches the resonant frequency due to component tolerances. To address this challenge, this paper proposes a parameter-mismatch insensitive cascaded POL converter by integrating a BUCK stage with a cascaded voltage divider (CVD). By introducing an auxiliary resonant branch, a multi-resonant operation is established, enabling the residual inductor energy caused by component variations to be transferred to the output during the dead time with virtually eliminated hard-switching losses. Consequently, precise matching between the switching frequency and the resonant frequency is no longer mandatory. A 12 V-to-1 V/30 A GaN-based prototype was developed to validate the theoretical analysis. Experimental results demonstrate that the proposed converter maintains high efficiency under a ±10% component variation and achieves robust voltage regulation and fast transient response, making it highly suitable for high-current data center applications.
Dejun Ba, Yihe Wang, Qi Cao et al.· Energies· 0 citations
This article proposes an isolated ultra-flat DC–DC converter architecture capable of directly converting high-voltage distribution rails (15–150 V) into regulated sub-1 V outputs with extremely high voltage conversion ratio. The solution is based on a resonant single-transformer structure specifically designed to enable large step-down operation while minimizing conduction path complexity. A 12:1 turns ratio with a single-turn secondary and reduced primary turns allows high gain realization using only one magnetic component and a minimized number of series devices along the main current path. The complete hardware implementation achieves a total height of 3.5 mm, making it compatible with surface power delivery and direct-to-chip integration constraints. An improved version incorporating a secondary-side active clamp is introduced to enhance controllability and transient behavior without increasing magnetic complexity. Both implementations are experimentally validated and quantitatively compared under equivalent operating conditions. The results demonstrate the feasibility of achieving extreme gain, wide gain variation, and ultra-low-profile integration using a single-magnetic isolated architecture suitable for future high-performance computing and AI processors.
Pablo Mazariegos, Javier Goicoechea, Cristina Martos-Contreras et al.· IEEE transactions on power e...· 0 citations
