It is argued that future progress will depend on cross-layer co-design rather than isolated optimization of devices, circuits, or architectures rather than isolated optimization of devices, circuits, or architectures.
As computational demands from artificial intelligence increase, traditional von Neumann architectures face memory wall bottlenecks while CMOS technology approaches physical limitations defined by Moore’s law and Dennard scaling. This entry examines memristor-based logic circuits as potential solutions to overcome these...
Zhipeng Liao, A. Jabir, Guang-Yu Xue et al.· Encyclopedia· 0 citations
This work presents a schematic-level digital near-memory computing architecture based on a 1-Transistor-3-Resistor (1T3R) bit-slicing scheme for 3-bit signed weight storage and indicates that the proposed architecture can maintain functional classification capability under 3-bit weight and 2-bit input constraints.
Zeyuan Hou, Xiao-Meng Wang, Yang Yi· Journal of Electronics and E...· 0 citations
Moving data between memory and processing units has become a major cost in neural network computing. Memristive crossbars address this cost by retaining model parameters as conductance states and performing parallel multiplication and accumulation within the array. This review examines how that physical operation is tr...
Chao-Yang Dong, Xuan Xie, Jian-Jun Chen et al.· Electronics· 0 citations
The escalating computational demand of modern AI is increasingly constrained by the data-movement overhead of von Neumann architectures, motivating memristor-based compute-in-memory (CIM) as an energy-efficient alternative. Yet extending CIM to reliable analog computation remains difficult because practical memristor a...
Yi-Fei Yu, Ji-Chang Yang, Zi-Jian Ye et al.· npj Unconventional Computing· 0 citations
The exciting potential of memristor-based components of neuroelectronics as the building blocks for a new era of artificial intelligence hardware, capable of surpassing current computational limitations, as well as their role in the ongoing transition to hybrid intelligence based on the symbiosis of electronic and biol...
A. Mikhaylov, S. Shchanikov, M. Koryazhkina et al.· Electronics· 0 citations
A comprehensive hardware-aware design framework for systematically mapping algorithmic workloads onto IMC architectures, using the discrete Fourier transform (DFT) as a case study and a novel mapping scheme that reduces energy consumption per computation by 53% compared with conventional mapping techniques is introduce...
Sofia Tatidis, P. Nielsen, Liang Liu et al.· 0 citations
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