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A 2-Block Architecture for Real-Time EEG Gait Decoding: A Pilot Study

Aug 2026 · 0 citations · 23 references
Computer Science Engineering

TL;DR

A 2-block Brain-Computer Interface architecture is proposed: a trainable session-specific Feature Extraction Block with real-time artifact suppression and multi-domain feature extraction, coupled with a Decoder Block built on a novel Polynomial Time-Varying Layer (PolyTVL)+LSTM for four-state gait classification.

Abstract

Closed-loop lower-limb exoskeleton control via Electroencephalography (EEG) remains limited by motion artifacts, low signal-to-noise ratio, and binary gait formulations that fail to capture full cortical gait complexity. We propose a 2-block Brain-Computer Interface (BCI) architecture: a trainable session-specific Feature Extraction Block with real-time artifact suppression and multi-domain feature extraction, coupled with a Decoder Block built on a novel Polynomial Time-Varying Layer (PolyTVL)+LSTM for four-state gait classification (Stand, Initiate, Execute, Terminate). Ablation confirmed v01 (PolyTVL+LSTM) outperformed all variants (validation MCC: 0.435, gap: 0.187), with consistent EEG feature discriminability across ROIs and sub-bands (p<0.05). Closed-loop deployment with v01 achieved 55.3% (Rex-assisted) and 52.7% (volitional) gait initiation success, with a mean end-to-end processing time of 70.5~ms (+/-41.5), validating real-time feasibility in this pilot study.

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