A Comparative Analysis of Power-Delay-Area Improvements Between Traditional Heuristic and AI-Driven Electronic Design Automation Techniques

Abstract

This paper presents a conceptual literature review and qualitative comparative synthesis of two major families of Electronic Design Automation (EDA) logic-optimization techniques: modern classical heuristic logic synthesis, grounded in scalable multi-level DAG-based optimization frameworks (Mishchenko et al., 2018; Amaru et al., 2016) and heuristic two-level logic minimization for large Boolean functions (Nazemi et al., 2021), and machine-learning-guided EDA workflows, represented by AI-driven logic gate synthesis (Astillero, 2026), reinforcement-learning-guided logic synthesis (Peruvemba et al., 2021), deep-learning-based logic optimization (Haaswijk et al., 2018), and graph-neural-network-based pre-routing timing prediction (Guo et al., 2022). Rather than reporting a new empirical benchmark, this review normalizes the direction and relative magnitude of Power, Performance, and Area (PPA) outcomes reported across this literature into a common qualitative baseline. The synthesis indicates that machine-learning-guided techniques can provide comparable or greater reported PPA benefits than classical heuristics, particularly for logic-reduction and timing-related applications, but these benefits are coupled with additional model-training overhead and sensitivity to the circuits and data used for training.