Design and Performance Analysis of QCA-Based BCD Adder Circuits for Energy-Efficient 6G Nanoscale Computing Systems

Abstract

Sixth-generation (6G) communication technologies are projected to enable exceptionally low-latency services, massive device connectivity, edge intelligence, and real-time processing of more complicated data. However, meeting these requirements using conventional technology is challenging because continued transistor scaling is associated with increased leakage current, power density, heat generation, and fabrication complexity. Emerging nanoscale computing technologies, particularly quantum-dot cellular automata (QCA), provide a promising alternative by enabling binary information processing through electronic interactions between neighboring cells rather than conventional current-driven switching. In this study, several QCA-based arithmetic and logic circuits are designed, including a fault-tolerant full adder (FA), 4-bit and 8-bit ripple-carry adders (RCA), and a binary-coded decimal (BCD) adder architecture. The proposed BCD adder performs binary addition and activates a decimal correction stage whenever the intermediate result exceeds nine or produces a carry-out. The circuit structures are enhanced to reduce cell count, occupied area, propagation delay, and energy dissipation while maintaining reliable signal transmission. The results demonstrate the potential of the proposed QCA arithmetic circuits as compact and energy-efficient computational components for future 6G edge devices, nanoscale processors, and communication systems.