Carrier Mobility Enhancement in Two‐Dimensional Semiconductor

Abstract

Continued dimensional scaling of silicon‐based CMOS technology is approaching fundamental physical limits, with degraded carrier mobility and increasingly severe short‐channel effects posing major challenges to further device scaling. Two‐dimensional (2D) semiconductors, characterized by atomically thin bodies and chemically passivated, dangling‐bond‐free surfaces, provide exceptional electrostatic gate control and have thus emerged as compelling candidates for channel materials in next‐generation integrated circuits. Yet, experimentally measured carrier mobility in 2D FETs often remains far below their phonon‐limited theoretical values because carrier transport is strongly affected by extrinsic scattering sources, including charged impurities, surface optical phonons, dielectric disorder, trap states, and Fermi‐level‐pinned contact barriers. This review provides a systematic and critical assessment of recent advances in mobility enhancement strategies for 2D semiconductor‐based field‐effect transistors (FETs). We begin by elucidating the distinctive carrier transport physics inherent to the strict 2D limit. We then examine six major classes of strategies: (i) defect suppression and atomic‐scale repair, (ii) contact interface engineering, including work‐function tuning and van der Waals integration, (iii) charged impurity passivation combined with high‐κ dielectric integration, (iv) controlled uniaxial and biaxial strain engineering, (v) heterostructure design and band alignment optimization, and (vi) emerging device architectures and electrostatic or doping modulation schemes. For each strategy, we summarize the underlying physical mechanisms, discuss representative experimental and theoretical advances, and compare key performance metrics, including peak field‐effect mobility, on‐state current density, and so forth. Finally, we discuss remaining scientific and technological challenges, including wafer‐scale material uniformity, scalable and CMOS‐compatible processing, reliable low‐resistance contact, and heterogeneous integration, and we outline future directions toward the practical deployment of 2D semiconductors in high‐performance and energy‐efficient electronic systems.