Presto: Hardware Acceleration of Ciphers for Hybrid Homomorphic Encryption

Abstract

Hybrid homomorphic encryption (HHE) combines specialized symmetric ciphers with homomorphic encryption to reduce ciphertext expansion and client cost. For highest throughput/energy for edge deployments, we present Presto, the first FPGA accelerators for the two known CKKS-targeting HHE ciphers, HERA and Rubato. Presto is throughput-optimized, with energy efficiencies due to utilization gains. It uses a deeply overlapped pipeline for key scheduling, MixRows/MixColumns (MRMC), and the nonlinear layer, and boosts utilization through batched multi-key execution and pipelined Barrett reduction. It resolves two major bottlenecks: data-ordering stalls in MRMC and expensive round-constant sampling. Stalling is removed by alternating state orientation that exploits MRMC's transposition-invariance. Round-constant sampling is hidden via an AES XOF producer-consumer side pipeline. Implemented on an Ultra96-V2 FPGA, and integrated with the novel GPU-based server-side HHE, Presto improves throughput over CPU-only software by 71× for HERA and 44× for Rubato, while reducing energy per key by 37× and 22×, respectively.