Development of a method for optimal computation distribution in digital signal processing algorithms for heterogeneous systems-on-chip

Abstract

The object of research is the process of hardware/software co-design and computational load distribution for digital signal processing (DSP) algorithms in heterogeneous systems-on-chip (SoC). The problem solved in this work is the lack of effective methods for distributing computational functions at the early design stages of architectures combining a processing system (PS) and programmable logic (PL). Unlike approaches relying on intuitive distribution or a full synthesis cycle, causing hardware overhead or timing violations, a hardware/software co-design method for DSP algorithms which accounts for the technological parameters of the SoC platform and enables analytical selection of the optimal implementation route at the system level, has been developed. A computing distribution model for the PS and PL parts is proposed, integrating platform characteristics, design object parameters, and specification constraints. A system of sub-criteria has been defined to minimize algorithm execution time under strict platform constraints. Based on these criteria, quantitative thresholds have been established to choose between software, hardware, or hybrid implementation routes, depending on the size of the design object. Using the Zynq-7000 as an example, it is proven that software implementation on the PS side is effective for small- and medium-sized objects, while transitioning to the PL part is critical for large-scale objects. It was established that transitioning from native code to high-level synthesis (HLS) and structural C code optimization strategies (specifically the C2 method) improves system metrics, cutting execution time in half while reducing resource utilization by 30%. The method is recommended for designing embedded real-time DSP systems, processing media streams, analyzing high-dimensional sensor data, and creating intelligent decision support systems.