Design, Stability Improvement, and Scaling of a 4-Transistor Static Latch for Digital Compute-in-Memory
TL;DR
This work presents a novel standard cell-compliant static latch that can be placed alongside digital logic and investigates the use of backgate biasing to improve system stability, and draws a comparison between the 22 nm implementations from the original work and the 12 nm implementation, indicating that moving to finFET technologies can also improve cell stability.
Abstract
As data-driven applications grow in importance, several concerns have emerged regarding cloud computing. While cloud computing still offers superior performance, issues such as latency, security, and limited internet availability prevent many applications from adopting modern algorithms. Recently, edge computing has therefore gained traction. In edge computing, the computation is performed entirely on the local device, circumventing the need for internet access and cloud connectivity. Many edge devices are battery-powered and have only a limited power budget. Edge computing therefore focuses on extremely power-efficient operation. Memory movement represents a significant contribution to overall power use. A common method to reduce this overhead is Compute-in-Memory (CIM). While CIM research was initially predominantly driven by analog computing concepts, many advantages of digital computation can also be leveraged for CIM, making digital CIM an attractive alternative. One disadvantage of digital CIM lies in its comparably large memory footprint. In this work, we extend our prior work, which presented a novel standard cell-compliant static latch that can be placed alongside digital logic [1]. The bitcell achieves latching behavior with only four transistors and offers a 73% smaller footprint compared to a standard latch. Our prior work focused on fault mechanisms of the bitcells, as well as the implications of using the cell in system level, given comparably high error rates. In this work, we reiterate our previous findings and investigate the use of backgate biasing to improve system stability. We perform simulations that show improvements of 2.25x and 15x in static noise margin (SNM) and data retention, respectively. Additionally, we perform silicon measurements also indicating improvements in cell stability. To investigate the scaling potential, we transfer the design to a design-rule-clean layout in a commercial 12 nm finFET technology. We finally draw a comparison between the 22 nm implementations from our original work and the 12 nm implementation, indicating that moving to finFET technologies can also improve cell stability.
