Difference Amplified Controllability and Memory Alignment Based Hardware Trojan Detection Using Unsupervised Ensemble Algorithm

Abstract

Hardware Trojans (HTs) are malicious modifications that are inserted into integrated circuits (ICs) during design or fabrication, causing severe security threats including data leakage, functional disruption, and denial of service. Detection is particularly difficult due to the absence of labeled training data, high circuit complexity, and elevated false positive rates in existing methods. This paper proposes an unsupervised pre-silicon Hardware Trojan detection framework integrating different stages: structural and testability feature extraction from gate-level netlists, Difference Amplified Controllability (DAC) transformation, Pseudo-Normal Residual (PNR) analysis, memory alignment, DBSCAN-based clustering, Suspicious Circuit Block (SCB) partitioning, and a weighted ensemble of four unsupervised anomaly detectors — Isolation Forest, Local Outlier Factor (LOF), One-Class SVM, and Principal Component Analysis. The framework is validated on ten Trust-Hub benchmark circuits including the S38417, S35932, S38584, and S15850 circuits and its different Trojan variants. Results show that DAC amplification improves feature separability, memory alignment captures multi-feature deviations missed by PNR residual methods, and a combined multi-circuit dataset achieves improved generalization with stable F1 scores across structurally diverse circuit families.