Test-Oriented Taxonomy and Full-Stack Verification Flows for Digital Processing-Near-Memory Systems

Abstract

Digital Processing-Near-Memory (PNM) reduces the energy and latency of data movement by placing programmable digital logic close to memory arrays or memory controllers. However, existing PNM discussions often mix heterogeneous integration choices, memory media, and workloads, making the corresponding test requirements difficult to compare. This paper presents a test-oriented taxonomy for digital PNM systems and connects each architecture class with concrete fault sources, access mechanisms, and workload-level oracles. The taxonomy covers 3D-stacked DRAM PNM, planar DRAM/CXL-attached PNM, eNVM-based PNM, and security-oriented PNM for cryptographic and private-query workloads. Based on this mapping, we propose a full-stack verification methodology that combines pre-silicon UVM and virtual-prototype verification, DFT and BIST insertion, post-silicon ATE and bench characterization, reliability qualification, and application-level benchmarking. Three reference flows are further instantiated for HBM-PIM, CXL-PNM, and eNVM-PNM to show how conventional memory, logic, 3D-IC, and system validation practices must be composed for PNM-specific observability, controllability, and end-to-end correctness.