Hardware Acceleration of CRYSTALS-Dilithium for Secure Booting on Shakti C-Class RISC-V Processor

Abstract

Post-quantum cryptography (PQC) architectures are becoming essential for secure boot mechanisms in embedded RISC-V systems due to emerging quantum threats against RSA and ECDSA in the coming years. The paper presents a hardware-accelerated CRYSTALS-Dilithium implementation on India's indigenous Shakti C-Class processor, an ISRO-qualified core optimized for low boot latency in resource constrained environments. Modular AXI4-Lite accelerators for the number theoretic transform (NTT), inverse NTT polynomial multiplication, and Keccak hashing were developed and integrated into the Shakti SoC fabric. The proposed architecture supports a practical secure boot flow that combines AES-256 decryption with Dilithium Level-2 signature verification. The design was validated through Verilator cycle-accurate simulation and synthesized using Vivado targeting Artix-7 devices. Experimental results provide roughly a 69% reduction in verification cycles, in reference to the software baseline. Keccak acceleration alone provides 60% cycle savings, while the complete accelerator suite incurs only 4% LUT overhead while meeting 100 MHz timing closure.